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AR# 35976 Design Advisory for MIG, MPMC Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality (software/IP update required)

Description

A reset issue exists with the Spartan-6 FPGA BUFPLL_MCB block that is used to generate the system clocks for MCB designs. When a reset is issued to a MIG or MPMC generated MCB design, approximately one out of a few thousand resets can result in the clocks generated by the BUFPLL_MCB block not restarting, which causes the MCB to stop operating. Once this situation occurs, additional resets do not resolve the problem. A power cycle/reconfiguration of the device is needed.

Solution

To quickly determine if a board level reset might be related to this issue, probe the CK clock going to the memory on the board. If the clock is toggling, the configuration is not affected by this issue.

Xilinx has determined the root cause of this issue and is currently putting together an ISE software and MIG rtl fix.

Root Cause - The asynchronous nature of the reset can lead to the BUFPLL_MCB entering an undefined state when used in its current software configuration.

Resolution - To resolve this issue, updated ISE software includes a new BUFPLL_MCB model with additional pins. New MIG/MPMC design files connect the additional pins appropriately to ensure that the BUFPLL_MCB always resets correctly. Thishas beenresolved in ISE tools 12.2/MIG 3.5.

If additional help is required, please open a Web case.

To see a list of other recent and important MCB Answer Records, refer to:

(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB,RLDRAMII, QDRII+, QDRII, DDRII cores
(Xilinx Answer 34587) MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1
(Xilinx Answer 34609) 12.x EDK - Master Answer Record List

NOTE: If you received the following error message in ISE software 12.2 or higher, see (Xilinx Answer 41985):

ERROR:PhysDesignRules:2268 - Invalid configuration (incorrect pin connections and/or modes) on block:<hierarchy/memcx_infrastructure_inst/BUFPLL_MCB_INST>:<BUFPLL_MCB_BUFPLL_MCB>. In order to ensure proper reset behavior, the GCLK, LOCKED and LOCK pins all need to be connected appropriately. Please see AR#35976 for specific details.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
41985 MIG, MPMC Spartan-6 MCB - ISE error message: " In order to ensure proper reset behavior" N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42024 MIG 7 Series DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM? N/A N/A
37498 MIG Design Assistant - Spartan-6 Core Functionality N/A N/A
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A
34263 Xilinx MIG Solution Center - Documentation N/A N/A

Actions

AR# 35976
Date Created 06/11/2010
Last Updated 07/17/2012
Status Active
Type Design Advisory
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG
  • Multi-Port Memory Controller (MPMC)
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