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AR# 35978 Design Advisory for MIG, MPMC Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs

Description

The Spartan-6 FPGA Memory Controller Block (MCB) can exhibit intermittent data errors on the last word of a memory READ burst due to incorrect bitstream programming of some elements of the I/O. All users of the MCB that have generated a Spartan-6 FPGA MIG or MPMC bitstream with ISE 12.1 or earlier version of the Xilinx software must regenerate their bitstream to resolve this issue.

Solution

Xilinx has determined the root cause for this issue and is making the necessary bitstream programming changes.
  • Root Cause - Incorrect bitstream programming within the I/O can cause intermittent data errors on the last word of a READ burst.
  • Resolution- A bitgen patch for the ISE 12.1 tools is provided in the link below. This patch allows the necessary bitstream changes to be implemented by regenerating a bitstream from an existing ncd file. Installation steps for the patch are detailed in a readme.txt included with the zip file. In ISE 12.2 software (release date end of July), the new bitstream programming will be implemented by default.

If you are experiencing this issue and additional help is required, please open a webcase.

To see a list of other recent and important MCB Answer Records, refer to:
(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores
(Xilinx Answer 34587) MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1
(Xilinx Answer 34609) 12.x EDK - Master Answer Record List

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A
34587 MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37498 MIG Design Assistant - Spartan-6 Core Functionality N/A N/A
42024 MIG 7 Series DDR3 - What is the recommended trace impedance between the FPGA and the DDR3 SDRAM? N/A N/A
34263 Xilinx MIG Solution Center - Documentation N/A N/A
33566 Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB, RLDRAMII, QDRII+, QDRII, DDRII cores N/A N/A

Actions

AR# 35978
Date Created 06/11/2010
Last Updated 08/02/2012
Status Active
Type Design Advisory
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG
  • Multi-Port Memory Controller (MPMC)
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