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AR# 36008 Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.3 and v1.3 rev 1 Core is not linking up reliably on ES (engineering sample) silicon using ISE 12.1 and ISE 11.5 or later software

Description

Due to the automatic insertion of the MMCM calibration block that occurs in ISE11.5 and ISE 12.1 tools, the v1.3 or v1.3 rev 1 core might notreliably link up. This could occur on the ML605 board as well as your own board.

Solution

This issue is fixed in the v1.3 rev 2 patch. Refer to (Xilinx Answer 34279) for the patch.

Revision History
08/10/2010 - Referred to AR 34279.
07/01/2010 - Added v1.3 rev 2 information
06/08/2010 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33276 Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33276 Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Actions

AR# 36008
Date Created 06/08/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
Tools
  • ISE Design Suite - 12.1
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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