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AR# 36019 Virtex-6 FPGA Integrated Block for PCI Express - Coregen allows generating a x8 Gen 2 design for the XC6VLX550T-2; But this is not supported

Description

In ISE software 12.1, the v1.5 core allows the user to generate a x8 Gen 2 design for the XC6VLX550T-2. The problem is that x8 Gen 2 is not supported in this part for a -2 speedgrade. Implementing will likely result in timing failures.

Solution

There is no workaround for this since there is no -3 speed grade currently available for this part.

Revision History
06/03/2010 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35322 Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A

Actions

AR# 36019
Date Created 06/03/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
Tools
  • ISE Design Suite - 12.1
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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