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AR# 36049

Design Assistant for PCI Express - TRN User Application Interface Questions

Description

This answer record is the starting point for questions regarding the TRN interface for Xilinx cores for PCI Express.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution


See (Xilinx Answer 36075) regarding packet straddling on the Virtex-6 x8 Gen 2 TRN interface.
See (Xilinx Answer 37042) regarding if the Virtex-6 x8 Gen 2 TRN interface is still used when the core trains to Gen 1 speed.
See (Xilinx Answer 38542) regarding latency through the TRN interface.
See (Xilinx Answer 38552) regarding reasons why trn_tdst_rdy_n may deassert indefinitely.
See (Xilinx Answer 38661) regardingdeassertion of trn_tdst_rdy_n before accepting a complete TLP in V5 PCIe Block Plus core.
See (Xilinx Answer 34260) regarding why trn_terr_drop_n may assert?

Revision History
07/30/2011 - Added 38542, 38552, 38661, 34260.
08/13/2010 - Initial Release

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AR# 36049
Date Created 08/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • More
  • Virtex-6 SXT
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express