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AR# 36062 Design Assistant for PCI Express - Start here with questions about core functionality or protocol


This Answer Record is the starting point for questions regarding core functionality or protocol related items.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

User Application TRN Questions
See (Xilinx Answer 36049) regarding questions on the TRN interface

Transaction Layer Questions
See (Xilinx Answer 36591) regarding why completions for a string of memory reads may not be returned in the expected order.

Data Link Layer Questions
See (Xilinx Answer 36063) regarding why a NAK is sent for a previously ACKed sequence number.

Physical Layer Questions
See (Xilinx Answer 37817) regarding how a the core ignores TS1 reserved bits for the Integrated PCI Express Block for S6.

Configuration Space Questions
See (Xilinx Answer 36589) regarding how to disable the "Enable Relaxed Ordering" bit in the Device Control register.
See (Xilinx Answer 36593) regarding how to check negotiated link width and current link speed.
See (Xilinx Answer 36633) regarding how to find out the starting address of the BARs.
See (Xilinx Answer 37007) regarding the behavior of the unsupported request bit when cfg_err_posted_n is deasserted and cfg_err_ur_n is asserted.
See (Xilinx Answer 36595) regarding how the user application can implement items in the legacy or extended configuration space.
See (Xilinx Answer 36596) regarding the difference between MAX_READ_REQUEST_SIZE and MAX_PAYLOAD_SIZE.
See (Xilinx Answer 36365) regarding the timing for user configuration read.
See (Xilinx Answer 37180) regarding how to set the "Extended Tag Supported" bit in the Device Control register and support eight bit tags.
See (Xilinx Answer 37497) regarding how to set the "Target Link Speed" bits in the Link Control 2 register.

General Core Functionality and Protocol Questions
See (Xilinx Answer 36594) regarding how to configure the core in order to use MSI or Legacy Interrupt.
See (Xilinx Answer 36627) regarding the steps for debugging issues with generation of MSI/Legacy Interrupts.
See (Xilinx Answer 36325) regarding how to disable ASPM. See (Xilinx Answer 38064) regarding core behavior when multiple errors occur.
See (Xilinx Answer 38447) regarding Memory read returning 0xffffffff

Drivers
See (Xilinx Answer 37063) regarding questions about drivers.


Revision History
10/12/2010 - Added 37180, 37497
10/08/2010 - Added 38447, 36325, 37817, 38064
08/13/2010 - Initial Release
AR# 36062
Date Created 08/02/2010
Last Updated 10/13/2010
Status Active
Type
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
  • Spartan-6 FPGA GTP Transceiver Wizard
  • Endpoint Block Plus Wrapper for PCI Express
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