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AR# 36075 Design Assistant for PCI Express - 128-bit interface with packet straddling

Description

This answer record is the starting point for questions regarding the 128-bit interface and packet straddling.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

The x8 Gen 2 core uses a 128-bit TRN interface. Received packets may not always start on bits 128:121, but may start at other places in the 128-bit bus. These straddled packets can be interpreted using the trn_trem_n bus. See the core's User Guide (UG517) for more information on how to read the straddled packets in the "Receiving Inbound Packets" section. See (Xilinx Answer 35920) to help locate the correct User Guide. There is no option to have the core de-straddle packets for the user.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37042 Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed? N/A N/A
36049 Design Assistant for PCI Express - TRN User Application Interface Questions N/A N/A
35920 Xilinx Solution Center for PCI Express - Documentation N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 36075
Date Created 08/02/2010
Last Updated 03/04/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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