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AR# 36078

MIG v3.4-v3.5 Virtex-6 DDR3 - reset# should use LVCMOS15 instead of SSTL15


MIG v3.4-v3.5 Virtex-6 DDR3 FPGA designs use I/O Standard SSTL15 for "ddr3_reset_n", but the DDR3 JEDEC Specifications states that RESET# is a "CMOS rail-to-rail signal".

IBIS Simulations show that using SSTL15 results in voltage overshoot and that using LVCMOS15 is a better solution.


This is fixed in the 12.3 release of the software tools with MIG v3.6.

You can also work around the problem by manually changing the I/O standard in the UCF file to:

NET  "ddr3_reset_n"                             IOSTANDARD = LVCMOS15;

AR# 36078
Date 08/26/2014
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG
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