Prior to ISE software 12.2, Virtex-6 FPGA designs with compatible, but non-continuous banks might have a place error if the skipped banks do not satisfy DCI_Cascade banking rules. For instance, CONFIG DCI_CASCADE = "36 37 34 32"; can be used without including bank 35.
The following common error seen would be:
"ERROR:Place:1104 - The following banks: Bank XX, Bank XX, Bank XX, Bank XX have been constrained to implement DCI Cascade, but the IOs locked to these banks with incompatible VCCO"