I have generated a BSB design for a Spartan-6 FPGA SP605 board. The design was originally working, but after I changed the memory part of another DDR2 device, I got the following error.
ERROR:EDK:3193 - issued from TCL procedure
"::hw_mpmc_v6_00_a::syslevel_update_mem_cas_latency" line 76
C_MEM_CAS_LATENCY (IPNAME:mpmc, INSTANCE:MCB_DDR3) - Not able to find a
suitable memory CAS latency for frequency 400.0MHz (2500ps.) If this is your
intended clock frequency, please ensure you have set the
C_MEM_PART_CAS_[A-D], and C_MEM_PART_CAS_[A-D]_FMAX parameters correctly.
Please see the MPMC data sheet for more details on these parameters.
What does this mean, and how I can resolve it?
The reason for this error is because the memory device chosen is not capable of running at that high speed. One would have to either lower the memory frequency or choose another memory part that can run at that speed.
When in doubt of which memory device can be used for different frequencies, one could simply check the MPMC database file at the following location.