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AR# 36112 System Generator for DSP 12.1 - I am unable to meet timing with the clock enable (CE) nets in my System Generator design

Description

The CE nets have a very high fanout and fail to meet timing if register duplication does not occur. This should be done automatically by the tools but is currently failing in some designs specific to System Generator.

Solution


Beginning in 11.4, the max_fanout attribute does not always work to force register duplication. This can make timing on the CE nets very difficult for large System Generator designs.

For more details and a suggested work-around, see (Xilinx Answer 36478).

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AR# 36112
Date Created 07/02/2010
Last Updated 07/02/2010
Status Active
Type
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