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AR# 36134

EDK 12.1, XPS_INTC - "Place:644 - A clock IOB clock component is not placed at an optimal clock IOB site."


When external pins from an ISE software design are connected to the interrupt controller as edge sensitive interrupts, the tools fail in implementation without specific constraints on the signals.


The XPS interrupt controller is designed in a way suchthat the tools assume that edge triggered interrupt signals should be on clock routing resources. If the interrupts are not on clock capable pins the placer results in errors with a message similar to the following:

"Place:644 - A clock IOB clock component is not placed at an optimal clock IOB site. The clock IOB component<IRQ_SYNTH<0>> is placed at site <IOB_X2Y256>. The clock IO site can use the fast path between the IO and the Clockbuffer/GCLK if the IOB is placed in the master Clock IOB Site."

To fix this issue, apply the buffer_type synthesis attribute to instruct the tools to infer an ibuf rather than an ibufg. The attribute should be applied to the top level signal entering the design.

For more information and examples on how to apply this attribute, refer to the XST User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/xst.pdf

AR# 36134
Date Created 06/10/2010
Last Updated 12/15/2012
Status Active
Type General Article
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  • EDK - 12.1
  • Interrupt Control