"Place:644 - A clock IOB clock component is not placed at an optimal clock IOB site. The clock IOB component<IRQ_SYNTH<0>> is placed at site <IOB_X2Y256>. The clock IO site can use the fast path between the IO and the Clockbuffer/GCLK if the IOB is placed in the master Clock IOB Site."
To fix this issue, apply the buffer_type synthesis attribute to instruct the tools to infer an ibuf rather than an ibufg. The attribute should be applied to the top level signal entering the design.
For more information and examples on how to apply this attribute, refer to the XST User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/xst.pdf