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AR# 36137 Design Assistant for PCI Express - trn_reset_n (user_reset_out for AXI) is deasserting, but trn_lnk_up_n (user_lnk_up_n for AXI) is not asserting

Description


This Answer Record discusses what to consider if trn_reset_n (user_reset_out for AXI) is deasserted, but trn_lnk_up_n (user_lnk_up_n for AXI)is asserted.
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution


The signal trn_reset_n (user_reset_out for AXI)indicates the reset sequence is complete and assertion of(user_lnk_up_n for AXI) indicates the link is trained. If trn_reset_n is not deasserted, then go back to (Xilinx Answer 34873).
Iftrn_reset_n (user_reset_out for AXI)is deasserted andtrn_lnk_up_n (user_lnk_up_n for AXI) is not asserted, then the link training process is failing. There are many things to investigate when this happens.
First, verify if a warm reset solves the problem as described in (Xilinx Answer 34800).
Link training issues are almost always board and signal integrity related. It could be that the MGT options that control the Pre-Emphasis and Swing need to be adjusted, or you can also try using the RX Equalization options.
If this is a multi-lane link, the problem might be due to cross talk or noise with multiple lanes being active at the same time. Test for this by electrically isolating the upper lanes and allow it to train as a x1 link only. You can do this with an add-in card by taping off the upper lanes on the card using Scotch tape (see the PCI Express Card Electromechanical Specification for information on the definitions of the pins on the connector so you know what to tape off). Also, you could use a x1 adapter that fits between the slot and the card to force it to a x1 link only. If this solves the problem, the issue is most likely one of Signal Integrity (see the "Board Design Guidelines" chapter in the User Guide).
A link analyzer is also helpful to determine why link training is failing. Using a link analyzer, such as from Lecroy or Agilent, you can monitor the link training process and see at what point in the LTSSM the link is failing to train.

Revision History
10/11/2010 - Added AXI signal names
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34873 Design Assistant for PCI Express - Debugging System Recognition and Link Training Issues Using trn_lnk_up_n and trn_reset_n N/A N/A
34800 Design Assistant for PCI Express - Problems Associated with FPGA Configuration N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 36137
Date Created 08/03/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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