I have an FPGA design that fails noise analysis on banks that contain a Memory Interface Generator (MIG) core.
Should I be concerned about this?
Can I ignore these failures?
These failures can be safely ignored.
Address/Control pins and Data/Strobe pins will never switch at the same time, which Vivado or PlanAhead noise analysis does not consider.
In addition, MIG designs have been extensively characterized to not have Simultaneously Switching Noise (SSN) issues.
Note: This does not mean that a custom design with the same pin-out might not have SSN issues.
This applies only to designs generated from MIG.