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AR# 36141

Vivado - Can I ignore the noise failures on MIG designs?


I have an FPGA design that fails noise analysis on banks that contain a Memory Interface Generator (MIG) core.

Should I be concerned about this?

Can I ignore these failures?


These failures can be safely ignored.

Address/Control pins and Data/Strobe pins will never switch at the same time, which Vivado or PlanAhead noise analysis does not consider.

In addition, MIG designs have been extensively characterized to not have Simultaneously Switching Noise (SSN) issues.

Note: This does not mean that a custom design with the same pin-out might not have SSN issues.

This applies only to designs generated from MIG.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
31905 Simultaneously Switching Noise - Where can I find documentation on SSO/SSN? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40868 MIG Spartan-6 MCB - Simultaneously Switching Noise (SSN) Calculation N/A N/A
AR# 36141
Date Created 07/30/2010
Last Updated 07/08/2015
Status Active
Type General Article
  • PlanAhead - 11.1
  • PlanAhead - 12.1
  • PlanAhead - 13.1
  • Vivado Design Suite
  • MIG