Resolved Issues: (Xilinx Answer 33800) 11.4 PlanAhead - Elaboration fails with std_logic_vector(0:0).
(Xilinx Answer 34872) 12.1 PlanAhead - error [HD-EDIFIN 6] Unsupported Construct on or above linexx
(Xilinx Answer 34870) 12.1 PlanAhead - ERROR:sim - This core is only supported on Windows 32-bit operating system
(Xilinx Answer 35394) 12.1 PlanAhead - MIG cores cannot be re-generated from PlanAhead if copied over from another location
(Xilinx Answer 35393) 12.1 PlanAhead - Opens up looking gray and empty when RTL fails to elaborate
(Xilinx Answer 35390) 12.1 PlanAhead - Hangs when save is clicked multiple times
(Xilinx Answer 35743) 12.1 PlanAhead - Incorrect BIVB DRC errors from PlanAhead
(Xilinx Answer 36372) 12.1 PlanAhead - DRC errors reported on DIFF_SSTL15_T_DCI IOstandard
(Xilinx Answer 35991) 12.1 PlanAhead - The Apply button does not appear after changing the cost table
Known Issues: (Xilinx Answer 36249) 12.1 PlanAhead - Cannot print default IOstandards to the ucf;
(Xilinx Answer 36640) 12.1 PlanAhead - Why do my errors not get brought to the front after I select "Don't Show This Again"?
(Xilinx Answer 34793) 12.1 PlanAhead - Synthesis with a netlist as top level in an RTL Project
(Xilinx Answer 36643) 12.1 PlanAhead - Changing IP Catalog Location in the Project Settings does not apply when project is re-opened
(Xilinx Answer 36461) 12.1 PlanAhead - "Make Diff Pair" does not work on RTL projects
(Xilinx Answer 35917) 12.1 Virtex-6 PlanAhead - When I import placement, BUFGDLL is not a supported primitive
(Xilinx Answer 34869) 12.1PlanAhead - How do we change CORE Generator Project Options?
(Xilinx Answer 36251) 12.1 PlanAhead - Why am I allowed to change Slew and Drive attributes on input ports?
(Xilinx Answer 35397) 12.1 PlanAhead - PlanAhead cannot set KEEPER to an I/O port of Spartan devices
(Xilinx Answer 36196) 12.1 PlanAhead - The Project Settings dialog fails to retain backslashes in paths
(Xilinx Answer 34878) 12.1 PlanAhead - ERROR: [HD-UCFReader 1] Unrecognized symbol \/leaf_2\/cont_ram\/v16384x72/BU2132 found
(Xilinx Answer 36197) 12.1 PlanAhead - Making changes to the .ncd file in FPGA Editor does not mark Implementation out of date
(Xilinx Answer 34876) 12.1 PlanAhead - "RTL I/O PLanner view" errors on loc constraints
(Xilinx Answer 36036) 12.1 EDK - PlanAhead/ChipScope software flow is broken when there is an ICON in the EDK submodule
(Xilinx Answer 32378) 12.1 PlanAhead - What synthesis tools are supported within PlanAhead?
(Xilinx Answer 36363) 12.1 PlanAhead - When changing I/O attributes on a differential pair, changes are only reflected on the master
(Xilinx Answer 36242) 12.1 PlanAhead - How do I manually set the HDL compile order for XST when running synthesis in PlanAhead?
(Xilinx Answer 36641) 12.1 Partial Reconfig PlanAhead - Constraints on RM logic loaded when the RM is a black box are not applied