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AR# 36174 Design Assistant for PCI Express - Start here for questions regarding Synthesis or Implementation

Description

This Answer Record is a starting place for questions regarding core synthesis or implementation.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

For information on implementing the core in ISE Project Navigator, see (Xilinx Answer 35722).

For information on usage of GTP/GTX pin locations for PCIe Block in Virtex-6, Spartan-6, and PCIe Block Plus in Virtex-5 devices, see (Xilinx Answer 37517).

For information on "ERROR:ConstraintSystem:59 - Constraint
"core/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX" LOC" when targeting the ML605 board, see (Xilinx Answer 37947).

Revision History
08/13/2010 - Initial Release

Actions

AR# 36174
Date Created 08/03/2010
Last Updated 10/13/2010
Status Active
Type
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express
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