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AR# 36199

12.2 PlanAhead - Unable to generate VEO for CORE Generator cores after creating VHO file


I generated a core using the default settings HDL type and it generated a VHO file. Then, I opened the project settings, changed the IP Language to Verilog, and regenerated the core. I am expecting a VEO, but I still get a VHO.

Is this the expected behavior?


This is the expected behavior for 12.1 and 12.2; the HDL setting is defined when the IP is created for the first time. Starting in 12.3, the HDL setting is read when the IP is customized.
AR# 36199
Date 05/23/2014
Status Archive
Type General Article
  • PlanAhead - 12.1
  • PlanAhead - 12.2
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