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AR# 36208 Design Assistant for PCI Express - Simulation Questions Regarding Configuration Traffic

Description


This Answer Record identifies starting points to debug configuration related questions in simulation. However, much of this information is also true in hardware, but is more prevalent in simulation since the user has more control of the configuration process in simulation.
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

For information on why reading BARs returns all zeroes, see (Xilinx Answer 36215).
Forinformation on why no completions are returned for configuration reads or writes, see (Xilinx Answer 36209).

Revision History
10/11/2010 - Updated links
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38548 Design Assistant for PCI Express - Simulation Traffic Questions N/A N/A
36215 Design Assistant for PCI Express - Why does reading of BAR register return all zeroes? N/A N/A
36209 Design Assistant for PCI Express - Why are no completions returned when reading or writing the configuration space? N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 36208
Date Created 07/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • More
  • Virtex-6 SXT
  • Spartan-6 LXT
  • Less
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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