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AR# 36209 Design Assistant for PCI Express - Why are no completions returned when reading or writing the configuration space?

Description


Why are no completions returned for Configuration Reads or Writes during simulation?

NOTE: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution


Make sure that the cfg_gnt_n (tx_cfg_gnt AXI) signal is asserted to the core. This signal allows the user application to hold off the core's ability to send completions for incoming configuration reads or writes. However, if this signal is left floating or tied incorrectly, the user might inadvertently cause the block to not be able to respond to configuration transactions.

In hardware, this would most likely result in a system hang because it would result in a completion timeout.

Normally, the user ties this signal asserted. For more information on this signal and to access the User Guides, see (Xilinx Answer 35920).

Revision History
10/11/2010 - Initial Release

Actions

AR# 36209
Date Created 10/13/2010
Last Updated 10/13/2010
Status Active
Type
IP
  • Virtex-6 FPGA Integrated Endpoint Block for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express
  • Endpoint Block Plus Wrapper for PCI Express
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