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AR# 36211

MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2

Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.5 released in ISE Design Suite 12.2 and contains the following information:
  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

MIG v3.5 is available through ISE Design Suite 12.2.

For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4, and Virtex-5 FPGA, see the MIG User Guide:
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide:
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide and Datasheet:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf

Software Requirements
  • Xilinx ISE Design Suite 12.2
  • Synplify Pro C-2009.12 Support
  • 32-bit Windows XP
  • 32-bit Linux Red Hat Enterprise 4.0
  • 64-bit/32-bit Linux Red Hat Enterprise 4.0
  • 64-bit XP professional
  • 32-bit Vista business
  • 64-bit SUSE 10
  • 64-bit/32-bit Linux Red Hat Enterprise 5.0 support
  • 64-bit Windows Vista support
  • 32-bit SUSE 10 support
New Features
  • ISE Design Suite 12.2 software support
  • Support for Bank Sharing across multiple controllers for Virtex-6 DDR3 SDRAM and QDRII+ SRAM design
  • Support for 'Read UCF' and 'Save Pin Out' features in Pin selection for Virtex-5 and Virtex-6 FPGA families
  • Improved the efficiency in providing the Default Banks for Multi Controller designs of Virtex-6
  • Provided the indication of obsolete memory parts in the GUI for all the FPGA families
  • Support of 'Update Design' for Spartan-6 designs
  • Support of Defense-Grade Virtex-6Q, Defense-Grade Spartan-6Q, Defense-Grade Spartan-6Q Low Power FPGA families
  • Extended Mode support for Spartan-6 DDR3 SDRAM and DDR2 SDRAM designs
  • Modified the default RZQ and ZIO pins to be compatible across all the Devices in a Package and provided the selection of RZQ and ZIO pins in the GUI for Spartan-6 designs
  • Default bank selections for Virtex-6 single controller designs modified such that configuration banks (#24 and #34) are not used in most of the configurations
Resolved Issues
  • MIG User Guide
    • UG086: Added a section about "Changing Refresh Rate" for Virtex-5 DDR2 and DDR designs
      • CR 560488
    • UG406: Provided information about how to manually calculate the Latency when Fixed Latency Mode is unchecked for Virtex-6 RLDRAM II designs
      • CR 552795
    • UG406: Provided a section on how to change the core parameters to set up for a clock period half of the Memory interface
      • CR 550717
    • UG406: Information about the PHASE_DETECT parameter is added for Virtex-6 DDR2 SDRAM designs
      • CR 539657
    • UG406: Provided the description related to Verify UCF and its rules of Virtex-6 Designs
      • CR 555404
  • MIG Tool
    • (Xilinx Answer 35247) MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites
    • Provided the valid default memory part for all the Memory families
      • CR 554750
    • Removed requirement to select Example Design specific pins in the Pin Selection Feature
      • CR 546874
    • Separated to generate the batch files with .sh extension in Linux platform and with .bat extension in NT platform
      • CR 541860
    • Removed generation of Xilinx Reference Board designs through MIG and replaced with the appropriate website link to the design files
      • CR 540501
    • Resolved all the issues in verifying the pins in Pin Selection feature and provided updated errors upon selection of 'Validate' button
      • CR 554427
    • Provided the separate 'Create Custom Part' button beneath the memory part selection combo
      • CR 554249
    • Showing all the Data widths regardless of frequency and used the warning symbol if the data width is not supported for the selected frequency and memory part
      • CR 549006
    • Improved the pin allocation algorithm which in turn made possible to fit the Data and Address group signals in a single bank for DDR3 Virtex-6 designs
      • CR 538492
    • The datasheet.txt contains the information of all the pins used for each bank
      • CR 538474
    • MIG 3.4-Bank Selection Page doesn't allow all data signals to fit on Bank 33 and 32
      • CR 562097
    • There's no "pin compatible FPGAs" option for MCB design
      • CR 542584
    • Support for Bank Sharing across multiple controllers for Virtex-6 DDR3 SDRAM and QDRII+ SRAM designs
      • CR 528879
    • Provided the relative path of the mig.prj and xmdf.tcl file instead of absolute path in the out file created by MIG in order to re-customize the project in the both Linux and NT platforms
      • CR 554200
  • Virtex-6
    • (Xilinx Answer 35742) MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N
    • Resolved issues with multi-controller design simulations
      • CR 554750
    • Provided "Row Address" value selection of 16 in "Create Custom Part" option for DDR3 SDRAM designs such that 8Gb/4Gb parts can be created
      • CR 550470
  • Virtex-5
    • (Xilinx Answer 35248) MIG v3.4 Virtex-5 FPGA - All VHDL Example Design outputs using Synplify flow will fail in hardware
    • (Xilinx Answer 36335) MIG v3.3, v3.4 Virtex-5 DDR2 - Data corruption occurs at the beginning or end of a read burst
    • Stage 4 calibration training pattern sequence changed to EE (rise_data) and 11 (fall_data) to increase the calibration point timing margin
      • CR 559837
    • Provided an optional non-fifo interface for Address FIFO of QDRII SRAM design
      • CR 557817
    • Initialized the signal precharge_ok_cnt_r to ensure proper read behavior when a write has not yet occurred
      • CR 550687
  • Virtex-4
    • (Xilinx Answer 35291) MIG v3.4 - Virtex-4 - RLDRAMII - During simulation of the VHDL design iteration limit error occurs
  • Spartan-6
    • (Xilinx Answer 35978) MIG Spartan-6 MCB - Last word of read burst fails in hardware - bitstream update required for all MCB designs
    • (Xilinx Answer 35976) MIG Spartan-6 MCB - Design does not come out of reset and requires power-cycle to regain functionality - SW / IP update required
    • (Xilinx Answer 35818) Spartan-6 FPGA - Memory Controller Block (MCB) Performance Change for DDR2 and DDR3 interfaces
    • (Xilinx Answer 35044) 11.5/12.1 Spartan-6 Place - The clock placer is not accounting for the proper PLL_ADV to BUFFPLL_MCB connection in larger devices - Results in MIG/MPMC MCB Calibration Failures in Hardware
    • (Xilinx Answer 35499) MIG v3.4 Spartan-6 Traffic Generator - 128-bit Bi-Directional Port Example Design does not work in hardware
    • (Xilinx Answer 35250) MIG Spartan-6 MCB - MIG generated ise_flow.bat script file produces error during XST on Windows
    • (Xilinx Answer 35238) MIG v3.4 Spartan-6 MCB LPDDR - MIG generated ise_flow.bat script file is missing BitGen command to create a bit file
    • (Xilinx Answer 35245) MIG Spartan-6 MCB - User Interface cannot send commands until calibration completes (cal_done asserts)
    • (Xilinx Answer 35289) MIG v3.4, Spartan-6 FPGA LPDDR - When running the LPDDR design the traffic generator stops sending commands after long write bursts.
    • (Xilinx Answer 35290) MIG v3.4, Spartan-6L - Error when using Synplify Pro as a synthesis tool and targeting low power Spartan-6 devices
    • (Xilinx Answer 35485) MIG Spartan-6 - DDR2 - When using Synplify Pro for synthesis the design fails to send data in hardware.
    • (Xilinx Answer 35057) MIG v3.4, v3.4 - Spartan-6 - The MCB appears to violate the DDR2 Initialization Sequence
    • (Xilinx Answer 35869) MIG v3.4 - Spartan-6 - When simulating the example design with ModelSim PE I get an "Iteration limit" error.
    • Modified the frequency support range of LPDDR parts from 75-200 MHz to 30-200 MHz
      • CR 555983
    • Support of x16 Micron memory part is added for DDR3 SDRAM design
      • CR 551990

Known Issues

Virtex-6 MIG Designs
(Xilinx Answer 36554) MIG v3.5, Virtex-6 Multi-Controller Designs - Failure occurs in MAP when controllers require separate REFCLK frequencies (200 and 300MHz)
(Xilinx Answer 36477) MIG v3.5, Virtex-6 DDR3/QDRII+ - ERROR:Place:911 - CONFIG DCI_CASCADE = "34,35" is not a valid constraint.
(Xilinx Answer 36573) MIG v3.5, Virtex-6 DDR3/QDRII+ - Cannot place System Clock in between DCI Cascade Master/Slave banks

Spartan-6 FPGA MCB
(Xilinx Answer 37704) MIG v3.5 Spartan-6 MCB - Calibration does not complete (calib_done=0) when C_SIMULATION=FALSE
(Xilinx Answer 34046) MIG v3.3-3.5, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported
(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design
(Xilinx Answer 36575) MIG v3.0-3.5, Spartan-6 MCB - Refresh period is too large

Spartan-3 FPGA Designs
(Xilinx Answer 36553) MIG v3.5, Spartan-3A DSP DDR SDRAM - MAP fails on MIG output design when synthesized using Synplicity

Revision History
8/31/10 - Added Known Issue AR37704
AR# 36211
Date Created 07/02/2010
Last Updated 08/31/2010
Status Active
Type Release Notes