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AR# 36215

Design Assistant for PCI Express - Why does reading of BAR register return all zeroes?


During simulation, when I read BAR 0 it returns all zeroes. Why does it not return information about the size of the BAR?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.


During the customization process, the BARs are configured to a chosen size. This instructs the core to set some bits in the BAR as read writable and some bits as stuck at zero. Coming out of reset all of the read writable bits are 0. The system will then write all 1's to the BAR and then issue a read to the BAR. At that point, the data returned by the read completion will contain 1's in the bits that were read writable and 0's in the other bits. Using this information the system can determine how much space is being requested.

For example, if you requested a 1 MB BAR, then it will read FF00_0008. The first bit set to a 1 is bit 20 (2^20 = 1 MB). Note that the lower 4 bits have a different meaning since this is a Memory BAR.

During simulation the testbench must mimic this behavior otherwise the BAR will remain as all zeroes.

For more details see section 6.2.5 of the conventional PCI Local Bus Specification v3.0.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 36215
Date Created 07/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • More
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )