With ISE software version 12.2 or later, Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v1.4 configurations which use a GTX serial transceiver (including 1000BASE-X or SGMII physical interface configurations) fail in simulation or the Map stage of implementation with the following error:
DRC Error : If value of TX_BUFFER_USE is set to TRUE then value of POWER_SAVE[4] has to be set to 1 for instance GTXE1.
To correct this failure, POWER_SAVE should be set to "0000110100". This and other attributes have been updated in the GTX wrappers since the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v1.4 was released. The core's GTX wrappers can be upgraded to the latest v1.6 GTX wrapper (available starting in 12.2) using the following procedure:
1. Open the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v1.4 file /example_design/physical/v6_gtxwizard.xco in a text editor
2. Replace the line "CSET postemphasis_level=0000" with "CSET postemphasis_level=00000"
3. Replace the line "SELECT Virtex-6_FPGA_GTX_Transceiver_Wizard family Xilinx,_Inc. 1.5" with "SELECT Virtex-6_FPGA_GTX_Transceiver_Wizard family Xilinx,_Inc. 1.6"
4. Save and close the v6_gtxwizard.xco file
5. Open CORE Generator using the same project file which was used to generate the Ethernet MAC v1.4 wrapper
6. Select "Project" -> "Import Existing Customized IP", then locate and open the v6_gtxwizard.xco file you have just edited
7. In the customization GUI which opens, click "Generate" to generate the updated GTX wrapper
8. Overwrite the existing /example_design/physical/v6_gtxwizard.v[hd] and /example_design/physical/v6_gtxwizard_gtx.v[hd] files with the two files which have just been generated.