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When using a MIG or MPMC memory controller in Spartan-6 FPGA, memory failures (data errors) can occur after configuration or power consumption can be higher than expected.
Subsequent resets to the system without reconfiguration will work correctly and/or reduce the power consumption of the device.
This behavior can be seen on the Spartan-6 SP601 board or customer boards based on the SP601.
This behavior is only seen when all of the following conditions are true within the system:
The available Calibrated Input Termination option is enabled. This option is set through the MIG GUI, and is only available for DDR, DDR2, and DDR3 memory interfaces.
HSWAPEN is configured to provide internal pull-up resistors on all of the I/O pins prior to configuration, by tying it to ground.
A resistor-divider network is used to create the Vref rail.
A decoupling capacitor (or several) is placed on that Vref rail.
Note: LPDDR cannot use Calibrated Input Termination and does not use a Vref standard.
Therefore, LPDDR never exhibits this behavior.
All other MCB memory standards are subject to this behavior based on the above details.
This issue is caused by the Vref rail on the board getting pulled higher than the intended Vref level of Vcco/2 during the period prior to the device completing configuration, and then having this higher voltage present on the Vref rail after configuration completes.
This can happen when the HSWAPEN pin is grounded, which turns on internal pull-up resistors in all of the I/O pins- including the multipurpose Vref pins.
If the Vref supply is generated from a simple resistor-divider between Vcco and ground (instead of being generated from a regulator which may be able to sink current), the internal pull-up resistors in each Vref pin will essentially pull the Vref rail closer to Vcco by adding another pull-up resistor in parallel.
After the Spartan-6 is configured, the HSWAPEN pull-up resistors are shut off inside all of the I/O pins including the Vref pins, but any capacitance on the Vref rail will act to keep the higher voltage present until it has a chance to discharge.
The length of the discharge is based on the RC time constant of the resistor-divider and any capacitance on the rail - which will be dominated by any decoupling capacitors that are used.
Having this high Vref rail present when the Spartan-6 design begins to operate the MCB controller design can cause the Calibrated Input Termination circuit to not work correctly.
The end result could cause incorrect Input Termination values to be used on all of the DQ and DQS pins.
The following figures displays the Vref decay after configuration completes (DONE asserts) and the recommended work around (noted below) of holding sys_rst:
The following is the circuit diagram of the Vref resistor-divider circuit on the SP601 board:
After configuration, while the capacitor discharges, the MCB calibration can be skewed by the SSTL I/O standard on the RZQ/ZIO pins utilizing the Vref voltage.
This does not occur after a soft logic reset as the VREF has already discharged and is stable.
The SP605 is not affected as it uses a voltage regulator instead of a resistor network.
This issue can be resolved by holding reset after configuration until Vref is stable.
For designs on the SP601 board where modification to the code to hold the reset is not ideal, a manual reset after configuration also results in successful calibrated input termination and MCB operation.