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AR# 36325 Design Assistant for PCI Express - How to Disable ASPM?

Description

Active State Power Management (ASPM) is hardware autonomous power management. Each side of the link (receiver and transmitter) can enter the L0s power saving mode independently. When entering L0s, the transmitter transmits the electrical idle ordered set and then drives electrical idle. When moving from L0s back to L0, the transmitter sends the agreed number of FTS ordered sets to allow the receiver to obtain bit lock before moving back to L0 to resume normal link traffic. The number of FTS ordered sets required to obtain bit lock is advertised by the device during link training.

On devices and systems that comply with specficiation 2.1 or after, you can disable ASPM using the ASPM Optionality feature by setting the link control register ASPM support bits or bits 1 and 0 to 00b.

Endpoints in PCI Express systems prior to version 2.1 of the specification do not have the option to not support ASPM. In those machines, it is sometimes possible to disable the downstream ports option to enter ASPM in the BIOS.

How cana host machine be prevented from enabling Active State Power Management (ASPM) if there are no settings available to do so in the BIOS?

Note:This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

It is required for an endpoint device to at least support ASPM L0s state. The L1 state is optional. However, the downstream device can optionally disable ASPM on the endpoint. In some systems, youcan force this through a BIOS setting, but that is not always available.

If that option is not available, when generating the core, if the L0s Exit Latency in the Link Capabilities Register is set to a high value and the L0s Acceptable latency in the Device Capabilities register is set to a low value, the downstream port will disable ASPM in most cases because these settings are not achievable.

By default, the Xilinx core sets the L0s Exist Latency to the highest allowed value. You can set the L0s Acceptable Latency during the customization process in the CORE Generator GUI. Look for a drop down called "Acceptable L0s Latency" and set this to "Maximum of 64 ns".

To verify that ASPM is not enabled, check bits 1:0 of the connected downstream port's Link Control Register. A setting of 00b indicates that ASPM is disabled. For more information on these registers, see Chapter 7 of the PCI Express Base Specification.

Revision History:
7/26/2011 - Added information about v2.1 of specification
10/07/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36062 Design Assistant for PCI Express - Start here with questions about core functionality or protocol N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

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AR# 36325
Date Created 10/08/2010
Last Updated 02/04/2013
Status Active
Type General Article
IP
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  • Endpoint for PCI Express (Soft-IP)
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  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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