Serial RapidIO v5.5 - Example reset module might fail to completely reset the buffer

AR#	36342	Search For Another Answer
Topic	RapidIO
Last Updated	03/10/2011
Status	Active

Description

If the example reset module "rio_reset" generated with LogiCORE Serial RapidIO version 5.5 or earlier is used, after the link partner sends Link-Request/Reset-Device the buffer core might not be entirely reset, which could result in the stored data being sent again after reset.

Solution

The rio_reset module asserts LOG_RESET_N for 4 log_clk cycles. However, it needs to be asserted for 4 PHY_CLK cycles in order to reset the buffer completely. Since the PHY_CLK slows down during the reset, the LOG_RESET_LEN parameter must be changed in order to extend the reset.
This is only a problem for a x4 core because the clock slows down to 1/4 of the rate during reset. The Serial RapidIO x1 core is not affected.

The reset module should be changed :

Verilog

From:

// Reset lengths
localparam LOG_RESET_LEN = 4;

To:

// Reset lengths
localparam LOG_RESET_LEN = 12;

VHDL

From:

-- Reset lengths
constant LOG_RESET_LEN : integer := 4;

To:
-- Reset lengths
constant LOG_RESET_LEN : integer := 12;