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AR# 36347 12.1 EDK - I/O Buffers are inserted when using a EDK design as a sub-module in an ISE project


I have instantiated an EDK design as a sub-module in the ISE software. There are I/O Buffers automatically inserted on the ports from EDK design and thus fails synthesis.

What is the problem?


By default, XST would not insert IOBs if the EDK design is a sub-system. However, if it is a bi-directional I/O, XST will. For example of GPIO, when GPIO_IO is used, a IOBUF is inserted by PlatGen automatically. If you need to connect the GPIO port to other logic in the ISE design, the GPIO_IO_I, GPIO_IO_O and GPIO_IO_T port should be used.

There are also a few cores that have IOB instantiated inside of HDL code, such as MPMC. For those cores, they are supposed to be connected to external devices directly and should not be used for internal logic.
AR# 36347
Date Created 06/23/2010
Last Updated 06/23/2010
Status Active
Type
Tools
  • EDK - 12.1
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