I get the following error after making modifications to the custom IP as indicated by the EDK CTT guide and running through implementation:
Loading design module "../implementation/pwm_lights_0_wrapper.ngc"...
ERROR:NgdBuild:76 - File "../implementation/pwm_lights_0_wrapper.ngc" cannot be merged into block "pwm_lights_0" (TYPE="pwm_lights_0_wrapper") because one or more pins on the block, including pin "tst_out_vec<7>", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.
You may also receive the following similar error when doing an AXI design:
NgdBuild:76 - File "C:\My_projects\SP605_MB_AXI_Ext3_124\implementation\axi4_0_wrapper\axi4_0_wrapper_FIFO_GENERATOR_V7_2_2.ngo" cannot be merged into block "axi4_/si_converter_bank/gen_conv_slot[2].clock_conv_inst/gen_conv_write_ch.asyncfifo_aw/inst" (TYPE="axi4_0_wrapper_FIFO_GENERATOR_V7_2_2") because one or more pins on the block, including pin "dout<100>", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.
This error indicates that the modified core was not re-synthesized. Clean all the generated files in ISE and EDK software and rerun implementation to work around this issue.
In the case of the AXI design, re-running the "generate Netlist" function will allow the design to go through. The AXI problem will be fixed in 13.2.