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AR# 36359

13.1 EDK - ERROR:NgdBuild:76 - File "../implementation/pwm_lights_0_wrapper.ngc" cannot be

Description

I get the following error after making modifications to the custom IP as indicated by the EDK CTT guide and running through implementation:

Loading design module "../implementation/pwm_lights_0_wrapper.ngc"...
ERROR:NgdBuild:76 - File "../implementation/pwm_lights_0_wrapper.ngc" cannot be merged into block "pwm_lights_0" (TYPE="pwm_lights_0_wrapper") because one or more pins on the block, including pin "tst_out_vec<7>", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.

You may also receive the following similar error when doing an AXI design:

NgdBuild:76 - File "C:\My_projects\SP605_MB_AXI_Ext3_124\implementation\axi4_0_wrapper\axi4_0_wrapper_FIFO_GENERATOR_V7_2_2.ngo" cannot be merged into block "axi4_/si_converter_bank/gen_conv_slot[2].clock_conv_inst/gen_conv_write_ch.asyncfifo_aw/inst" (TYPE="axi4_0_wrapper_FIFO_GENERATOR_V7_2_2") because one or more pins on the block, including pin "dout<100>", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.

Solution

This error indicates that the modified core was not re-synthesized. Clean all the generated files in ISE and EDK software and rerun implementation to work around this issue.

In the case of the AXI design, re-running the "generate Netlist" function will allow the design to go through. The AXI problem will be fixed in 13.2.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
39843 13.x EDK - Master Answer Record N/A N/A
AR# 36359
Date Created 03/14/2011
Last Updated 02/05/2013
Status Active
Type Known Issues
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
Tools
  • ISE Design Suite - 12.1
  • EDK - 12.1