We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36372

12.1 PlanAhead - DRC errors are reported on the DIFF_SSTL15_T_DCI I/O standard


The MIG design completes implementation without any errors, but when I import the design into the PlanAhead tool and perform a DRC check, several errors are reported as follows:

"DCI Cascade 25{I/O Bank 25, I/O Bank 26} has multiple DCI I/O standards in a "Split" termination type. Only one DCI I/O standard is allowed in a cascade. The following DCI I/O standards were found: 1. "SSTL15_T_DCI": c0_ddr3_dq[0] c0_ddr3_dq[1] 2. "DIFF_SSTL15_T_DCI": c0_ddr3_dqs_p[0] c0_ddr3_dqs_n[0] c0_ddr3_dqs_p[1] c0_ddr3_dqs_n[1] c0_ddr3_dqs_p[2]"

What causes this error?


This is a known issue in the PlanAhead tool where it errors out on certain I/O standards (e.g., DIFF_SSTL15_T_DCI). There is nothing wrong with the design.

As long as the design implements fine, you can ignore this error.

This issue has been fixed in the 12.2 PlanAhead software release. Please upgrade to the newest version of software to avoid this issue.
AR# 36372
Date Created 07/07/2010
Last Updated 09/28/2010
Status Active
Type Known Issues
  • PlanAhead - 12.1