We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36412

Virtex-6 FPGA ML605 Evaluation Kit - Why does the BIST Flash test fail when I use the default board settings?


When I run the Flash test from the BIST application on my ML605 (or kit that includes the ML605), and the boards S2 settings are at the default setting ("001010") my test fails. 

Why does this happen?


S2 needs to be changed to "011010" (mode pins M2, M1, and M0 set to 110 for Slave SelectMAP mode) in order to communicate with the Platform Flash XL and pass the Flash test.

AR# 36412
Date Created 06/27/2010
Last Updated 01/12/2015
Status Active
Type General Article
Boards & Kits
  • Virtex-6 FPGA Connectivity Kit
  • Virtex-6 FPGA Embedded Kit
  • Virtex-6 FPGA ML605 Evaluation Kit