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AR# 36431

MIG/MPMC Spartan-6 MCB - Is there a preferred or required PLL location that should be used within the design?

Description


The MIG/MPMC MCB design uses a PLL to create the required design clocks. The ISE implementation tools automatically select and place the PLL location based on the I/O location of the PLL input clock. The implementation tools adhere to the Spartan-6 Clocking Regions, but might not select the preferred location for the MCB.What are the preferred PLL locations and how do I direct the implementation tools to select this ideal location?
NOTE: The PLL locations provided in this Answer Record are general recommendations for all Spartan-6 devices.However, for MCB designs targeting the larger Spartan-6 devices (LX75, LX75T, LX100, LX100T, LX150, LX150T), Xilinx strongly recommends specific PLL locations to ensure the highest margin across VCCINT variations (detailed below). The ISE implementation tools will select the recommended PLL in a future ISE software release.In the meantime, users should manually LOC the PLL location. This Answer Record provides information on which PLL is recommended and how to LOC its selection.

Solution


Recommended PLL Locations for MCB Designs
The Spartan-6 PLLs are located along a center column within the device. During characterization, Xilinx has found that the center most PLL within this column is the most ideal selection for the MCB designs. The center PLL has shown better jitter, clock skew, and duty-cycle distortion results in testing when compared to other PLL locations. These clock improvements result in the highest possible margin across VCCINT variations.Smaller Spartan-6 devices have enough available margin in the MCB design to cover the added jitter, clock skew, and duty-cycle distortion.However, as the devices get larger, the affects of these clocking degradations cut into needed margin. For this reason, the center PLL is preferred for all Spartan-6 MCB designs to ensure the highest possible margin, but is strongly recommended for the larger Spartan-6 devices (LX75, LX75T, LX100, LX100T, LX150, LX150T).
Because the PLLs are divided into top and bottom clocking regions, the preferred selection depends on whether the I/O for the PLL input clock is located in the top or bottom regions and the target Spartan-6 device.
LX9, LX16, LX25 and LX25T Preferred PLL Locations:
These smaller Spartan-6 devices only have two PLLs (one for the top region and one for the bottom).Therefore, the PLL selected by the implementation tools is the only available and therefore, preferred selection.
LX45 and LX45T Preferred PLL Locations:
These mid-sized Spartan-6 devices have four PLLs (two for the top region and two for the bottom). The PLLs in the center of these four are preferred for the MCB.
  • For clocks input on the top half of the device, the preferred PLL location is: PLL_ADV_X0Y2
  • For clocks input on the bottom half of the device, the preferred PLL location is PLL_ADV_X0Y1

LX75, LX75T, LX100, LX100T LX150, LX150T Strongly Recommended PLL Locations:
These large Spartan-6 devices have six PLLs (three for the top region and three for the bottom). The PLLs in the center of these six are strongly recommended for the MCB.
  • For clocks input on the top half of the device, the preferred PLL location is: PLL_ADV_X0Y3
  • For clocks input on the bottom half of the device, the preferred PLL location is PLL_ADV_X0Y2

Modifying MIG/MPMC Design to Ensure Preferred PLL Selection

To ensure the preferred or required PLL location is selected by the ISE implementation tools, a LOC constraint needs to be placed on the PLL.To add a LOC constraint, open the "example_design/par/example_top.ucf" or "user_design/par/core_name.ucf" file and add the appropriate LOC constraint.

Example:
INST "memcx_infrastructure_inst/u_pll_adv" LOC = "PLL_ADV_X0Y2";

NOTE: The 'x' in memcx should be replaced by the number in the instance name for your design (ie - "memc3_infrastructure_inst/u_pll_adv").
NOTE: The XxYx location above is only an example. Modify the values based on the guidelines provided in the Preferred PLL Locations for MCB Designs section of this Answer Record.

Additional Information:
  • The clocking structure for the MIG design is detailed in UG388- Designing with the MCB -> Clocking.
  • The Spartan-6 clocking regions can be viewed in UG382- Clock Resources -> Input Resources -> Figure 1-7: Spartan-6 FPGA Clock Pin Layout.
  • The available PLLs for each Spartan-6 device and their connection to BUFPLL_MCBs can be viewed in UG382 - Table 3-1: PLLs with Direct Connections to BUFPLL.

Linked Answer Records

Associated Answer Records

AR# 36431
Date Created 07/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • Multi-Port Memory Controller (MPMC)
  • MIG