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AR# 36475 MIG v3.0-3.4, Spartan-6 MCB - "ERROR:HDL Compiler:432 occurs when running MIG output"

Description


When I run a MIG v3.0-3.4 Spartan-6 design through Synthesis using ISE 12.2, the following errors occur:

"ERROR:HDLCompiler:432 - "Mig_v3_4/user_design/rtl/memc1_infrastructure.vhd" Line 293: has no actual or default value.
gclk is declared here locked is declared here

ERROR:HDLCompiler:854 - "Mig_v3_4/user_design/rtl/memc1_infrastructure.vhd" Line 102: Unit ignored due to previous errors.
VHDL file Mig_v3_4/user_design/rtl/memc1_infrastructure.vhd ignored due to errors"

Why do these errors occur?

Solution


The MIG design uses a BUFPLL_MCB component in the clocking structure for the MCB. This BUFPLL_MCB component had additional ports added in the ISE 12.2 software. Because of this model change, the MIG rtl generated prior to MIG v3.5 (ISE 12.2 release) does not connect these additional ports which causes these errors to occur during Synthesis.

The MIG v3.5 design must be ran with the ISE 12.2 tools. For additional information on the BUFPLL_MCB changes, see (Xilinx Answer 35976).

Actions

AR# 36475
Date Created 06/29/2010
Last Updated 06/29/2010
Status Active
Type
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG
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