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AR# 36503

MIG v3.4 Virtex-6 DDR3 - Cannot see phy_init_done go High in simulation

Description

When simulating a MIG v3.4 multi-controller design phy_init_done might fail to assert. This is a known issue andis fixed in MIG v3.5 (ISE 12.2 software).

Solution

To work around this issue, several lines in the testbench file (sim_tb_top.v) must be modified.

Specifically, inside the memory model instantiations, the variable "i" needs to be changed to "c0_i" (controller 0) and "c1_i" (controller 1) for the ck, ck_n, cke and cs_n connections.

For example, change the following:

.ck (c1_ddr3_ck_p_sdram[(i*C1_MEMORY_WIDTH)/72]),
to:
.ck (c1_ddr3_ck_p_sdram[(c1_i*C1_MEMORY_WIDTH)/72]),
Once you have changed allfour lines for each controller and re-simulated, the simulation completes successfully.
AR# 36503
Date Created 06/30/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG