The Memory Controller (MC) is responsible for receiving all requests from the User/Native Interface and storing them in a logical queue. In processing these requests, the MC ensures that all functional and timing requirements of the JEDEC standard/memory device are met. The MC only receives Read/Write commands, but must ensure that all required commands to complete Reads/Writes are sent (Refresh, Activate, Precharge). This section of the MIG 7 Series and Virtex-6 FPGA Design Assistant focuses on the architecture design of the DDR2/DDR3 MC. Please select from the options below for information related to your specific question.
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The following diagram is a visual picture of the MIG 7 series MC architecture design:
The following diagram is a visual picture of the MIG Virtex-6 MC architecture design:
For information on each of these blocks, see:
The 7 series Memory Controller is discussed in detail in the 7 Series FPGAs Memory Interface Solutions User Guide (UG586), see the Memory Controller section underDDR2 and DDR3 SDRAM Memory Interface Solution -> Core Architecture.
The Virtex-6 Memory Controller is discussed in detail in the Memory Controller Section Virtex-6 FPGA Memory Interface Solutions User Guide (UG406), see the Memory Controller section under DDR2 and DDR3 SDRAM Memory Interface Solution -> Core Architecture.
09/20/12 - Initial Release