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AR# 36545

Virtex-6 FPGA Integrated Block Wrapper PCI Express - Core never link trains when upper lanes are intentionally not used


Known Issue: v2.3, v2.2, v2.1, v1.7 v1.6, v1.5, v1.4, v1.3

If unused GTX serial pins are physically connected to one of the link partner's lanes, then the endpoint core will not train.

For example, if the board is routed as a x8, but only a x4 or x1 core is in use, it will not link train when plugged into a x8 capable slot.


This is a known issue if the design is implemented in ISE 13.1 or 12.x software. 

This is caused by the automatic Macro Insertion discussed in (Xilinx Answer 35055) 

When the automatically generated macro is inserted, this changes the detection termination and causes the link partner to not train properly with the endpoint. 

The macro will be updated to fix this issue in a future release.

This answer record will be updated once the macro is fixed to indicate the version of software including the fix.

To work around this problem, the RCV_TERM_VTTRX attribute of the unused GTXs must be changed to "FALSE" in FPGA Editor. 

This will change the termination so that the link partner will detect the correct amount of lanes.

This fix can only be made using FPGA Editor.

To make the appropriate changes in FPGA Editor, do the following:
  1. Open the routed NCD with FPGA Editor.
  2. Click on the editmode button (located on the right side of the screen) until the bottom right-hand corner of FPGA Editor indicates that it is now in Read Write mode. 
  3. Find the GTX component and click on it once so that it is now highlighted.
    Note: Make sure to not double-click the component. 
  4. Click on the editblock button and a new window will open.
  5. In this new window find the RCV_TERM_VTTRX attribute. 
  6. This attribute is a checkbox and is currently set to TRUE. 
    Change this to False and save this new NCD.

It is possible to automate the changes made within FPGA Editor by using the FPGA Editor Recording feature. 

Please see (Xilinx Answer 41222) for more details on this feature.

After saving the NCD, BitGen can generate the bit-file for the design.

Revision History
03/26/2011 - FPGA Editor recording script update.
02/10/2011 - Updated software versions affected
02/08/2011- Initial Release

Linked Answer Records

Master Answer Records

AR# 36545
Date Created 02/08/2011
Last Updated 03/18/2015
Status Active
Type Known Issues
  • Virtex-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LX
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 13.1
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • More
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • Less
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )