This issue occurs due to a pin update in the BUFPLL_MCB primitive for Spartan-6 FPGA. MIG supports Synplicity D-2009.12, however, the Synplify tools have not yet been updated to include the revised BUFPLL_MCB primitive. For details on the primitive change, see
(Xilinx Answer 35976).
Work-around:
Option1 Synplicity has created an updated BUFPLL_MCB model that can be downloaded from their support website. For instructions on using the updated model and a link to the model, please visit the following Solvnet Article:
https://solvnet.synopsys.com/retrieve/030979.html?otSearchResultSrc=advSearch&otSearchResultNumber=1&otPageNum=1Option2The Xilinx provided unisim BUFPLL_MCB model can be used if it is treated as a black box. This is an alternative work around to Option 1.
- Copy the BUFPLL_MCB.v file from $XILINX/verilog/src/unisims/BUFPLL_MCB.v and paste it in the MIG output "par" directory
- Update the model to add syn_black_box and translate_off/on constructs. This is shown in the BUFPLL_MCB.v file attached to this answer record (see link below).
- Update the script_synp.tcl file to compile the BUFPLL_MCB.v model: add_file -verilog "../par/BUFPLL_MCB.v" The updated script_synp.tcl is also attached for reference
- Execute the "ise_flow.sh" script (or "ise_flow.bat" in case of Windows) in the par directory.
This work-around will allow Synplify to synthesize the updated model. Similar steps can be followed for VHDL designs.
ZIP file with example files:
http://www.xilinx.com/txpatches/pub/applications/misc/36550.zip