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AR# 36552

Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - v1.3 Rev 2 Patch for ISE Design Suite 12.1


This is a patch for the Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express. This is the v1.3 rev 2 patch and is to be installed on ISE Design Suite 12.1. This patch resolves the following three issues:

CR 558043: Link Training Failure
Issue resolved where the link would not train or go to Gen 2 speed on cold boot. Rev 2.

CR 543565: MMCM VCO changed from 500 MHz to 1000 MHz.
The MMCM VC0 setting has been changed from 500 MHz to 1000 MHz due to new MMCM requirements Rev 1.

CR 551390: Fix for HDL compiler warnings.
Issue resolved where HDL compiler warnings were issued during Core Generation. Rev 1.

CR 558536: Disable Lane Reversal Setting for Endpoint Configuration.
Disable Lane Reversal Attribute setting on the Integrated Block has been set to FALSE for Endpoint Configurations, per CES Errata. Rev 1.

This patch is inclusive of the v1.3 rev 1 patch (Xilinx Answer 35422) and only this patch needs to be installed.

For other v1.3 known issues, see (Xilinx Answer 33276).


To download this patch, see (Xilinx Answer 34279). This Answer Record includes a list of all updates for the Virtex-6 FPGAIntegrated Block Wrapper.

Revision History
07/01/2010 - Initial Release

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 36552
Date Created 07/01/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
  • Virtex-6 LXT
  • ISE Design Suite - 12.1
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )