When a MIG v3.5 Spartan3A-DSP design is synthesized using Synplicity, the design fails during the MAP phase of ISE toolimplementation. The MAP failure is due to the "rst_iob_out" component not being packed into an IOB. This occurs because the clk180 signal is incorrectly pruned away in the tocontroller module. This issue only exists for Spartan-3A DSPDDR designs where the CAS Latency equals 2.5 and the synthesis tool selected is Synplicity. This issue exists in both Verilog and VHDL designs. There are no issues with XST designs.
To work around this issue, a syn_keep attribute must be added to the clk180 signal in "the *controller_0" module.
VHDL Work-around:
Add the following constraint in the *controller_0.vhd" module:
attribute syn_keep : boolean;
attribute syn_keep of clk180 : signal is true;
Verilog Work-around:
Update the following in the "*controller_0.v" module:
Existing code:
generate if(CAS_LAT_VAL == 3'b110) begin : FD_INST
(* IOB = "FORCE" *) FD rst_iob_out
(
.Q(rst_dqs_div_int),
.D(rst_dqs_div_d), .C(~clk)
)/* synthesis syn_useioff = 1 */;
Modified code:
wire clk180 /* synthesis syn_keep = 1 */;
assign clk180 = ~clk;
generate if(CAS_LAT_VAL == 3'b110) begin : FD_INST
(* IOB = "FORCE" *) FD rst_iob_out
(
.Q(rst_dqs_div_int),
.D(rst_dqs_div_d),
.C(clk180)
)/* synthesis syn_useioff = 1 */;