When a MIG design is generated with the System Clock group placed between Master and Slave DCI Cascade banks, PAR results in an error as follows:
"ERROR:Place:1104 - The following banks: Bank 24, Bank 25 have been constrained to implement DCI Cascade, but the IOs locked to these banks with incompatible VCCO:
Bank 24: IO Standard 0: Name = HSTL_I_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR = INPUT, DRIVE_STR = NR
IO Standard 1: Name = HSTL_I_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR = INPUT, DRIVE_STR = NR
Bank 25: IO Standard 0: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
IO Standard 2: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
IO Standard 3: Name = LVDS_25, VREF = NR, VCCO = NR, TERM = NONE, DIR = INPUT, DRIVE_STR = NR"
All DCI_CASCADE slave banks must have VCCO settings that are compatible with the VCCO settings of the DCI_CASCADE master bank. For more information on the DCI_CASCADE constraint, see the Constraint Guide. For more information on VCCO compatibility rules, see the architecture user's guide. An analysis can be done in PinAhead to evaluate which set of I/Os are locked to each of these I/O banks.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 36211 | MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 | N/A | N/A |