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When a MIG design is generated with the System Clock group placed between Master and Slave DCI Cascade banks, PAR results in an error as follows:
ERROR:Place:1104 - The following banks: Bank 24, Bank 25 have been constrained to implement DCI Cascade, but the IOs locked to these banks with incompatible VCCO:
Bank 24: IO Standard 0: Name = HSTL_I_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR = INPUT, DRIVE_STR = NR
IO Standard 1: Name = HSTL_I_DCI, VREF = 0.75, VCCO = 1.50, TERM = SPLIT, DIR = INPUT, DRIVE_STR = NR
Bank 25: IO Standard 0: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = OUTPUT, DRIVE_STR = NR
IO Standard 2: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
IO Standard 3: Name = LVDS_25, VREF = NR, VCCO = NR, TERM = NONE, DIR = INPUT, DRIVE_STR = NR
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
36211 | MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 | N/A | N/A |