We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36589

Design Assistant for PCI Express - How do I disable the "Enable Relaxed Ordering" bit (bit 4) in the device control register?


If enabled, how can the "Enable Relaxed Ordering" bit (bit 4) in the device control register be disabled? Is it necessary to disable it or can it be left as is?
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


The "Enable Relaxed Ordering" bit in the Device Control register comes out of reset as 0, but can be set to a 1 by the host. The user application cannot set or disable this bit. It does not really matter if the host sets this bit. It will not change the functionality of the core, but it does allow the user to set the Relaxed Ordering bit in the Attributes field of the TLP header. See sections, 2.4, and 7.8.4 of the PCI Express Base Specification.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 36589
Date Created 07/29/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )