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AR# 36591 Design Assistant for PCI Express - Why do completions for a string of memory reads not come back in the same order?

Description


When I send multiple memory reads from endpoint, I do not see the completions coming back in the same order. For example, I send MRd1, MRd2, MRd3, but the completions are returned out of order such asCplD2, CplD1, Cpld3. Is this expected behaviour?
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution


This is normal behaviour; see section 2.4 of the PCIe Base Specification for more information. Read completions for the same request must return in address order. Read completions for different request are allowed to be blocked or bypass each other. Also, remember a single read can result in more than one completion returned. The number of possible completions is determined by the RCB (Read Completion Boundary). Each outstanding memory read must have a unique tag. The completer must put this tag in the completions so the requestor can determine which completion associates with each outstanding read. For example, the following might occur:

MRD Tag 1 256 bytes
MRD Tag 2 256 bytes


The returned completions might be something similar to the following:

Cpld Tag 1 64 bytes
Cpld Tag 2 64 bytes
Cpld Tag 1 64 bytes
Cpld Tag 2 64 bytes
Cpld Tag 1 64 bytes
Cpld Tag 1 64 bytes
Cpld Tag 2 64 bytes
Cpld Tag 2 64 bytes

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36062 Design Assistant for PCI Express - Start here with questions about core functionality or protocol N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 36591
Date Created 07/28/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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