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AR# 36594 Design Assistant for PCI Express - How do I configure the core in order to use MSI or Legacy Interrupt?

Description


How is the core configured to use MSI or Legacy Interrupts?
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution


The use of MSI or legacy interrupts depends on whether the MSI enable bit is set in the MSI control register. The MSI enable bit is bit 0 of the MSI control register. The MSI control register is part of the MSI capability set. For more information on the MSI capability, see Chapter 6 of the PCI Local Bus Specification v3.0. The enable bit is set by a configuration write from the host. The user application cannot set this bit. Once set, the core asserts the cfg_msienable_n output to the user application.
If the MSI enable bit is not set then legacy interrupts are used by default.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36627 Design Assistant for PCI Express - Why Are Interrupts Not Transmitted N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
36062 Design Assistant for PCI Express - Start here with questions about core functionality or protocol N/A N/A

Actions

AR# 36594
Date Created 07/30/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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