The legacy PCI configuration space is located at offset 3Fh to FFh and is used to implement the various PCI capability sets. The Xilinx core's implement three capabilities which are the Power Management, MSI, and PCI Express capability. The rest of the space is not used. The PCIe extended configuration space starts at address 100h to FFFh. Depending on the core, some extended capability also implemented.
Users of the Virtex-5FPGAEndpoint Block Plus core cannot access the unused space for user purposes. However, Virtex-6 and Spartan-6 FPGA integrated block users can implement their own capabilities and have configuration transactions forwarded on to the user by enabling 'PCI Configuration Space Enable' and 'Extended PCI Configuration Space Enable' in the CORE Generator GUI (this is described in the User Guide).To help locate the correct User Guide, see
(Xilinx Answer 35920) Revision History
08/13/2010 - Initial Release