We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36596

Design Assistant for PCI Express - What is the difference between MAX_READ_REQUEST_SIZE and MAX_PAYLOAD_SIZE?


What is the difference between MAX_READ_REQUEST_SIZE and MAX_PAYLOAD_SIZE?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.


The maximum payload size (MPS) and maximum read request size register are found in the Device Control Register of the PCIe Capability Structure at offset 08h.

There are mainly two ways to find these settings in hardware.

One is to use a tool such as PCITree or lspci to read the contents of the Device Control register. For more information about these types of software tools see (Xilinx Answer 34806). The Device Control register may be located at different locations depending on the core you are using. To find the location of the Device Control register, you can either follow the linked capabilities list or look in the User Guide for the core in use. See (Xilinx Answer 35920) to help locate the correct User Guide. This information will be found the "Core Overview" section.

Another way to determine this information is to use the cfg_dcommand[15:0] output from the core to the user application.

Maximum Payload Size

The MPS register controls the maximum size of the data payload of a TLP. Although the PCI Express specification allows for payloads of up to 4,096 bytes, the specification says: Software must take care to ensure that each packet does not exceed the Max_Payload_Size parameter of any system element along the packets path. This means that every device in the hierarchy must use the same MPS setting, and the setting must not exceed the capability of any device within the hierarchy. Therefore, devices with high MPS capability are required to operate at lower MPS settings to accommodate the device with the lowest MPS capability. As a receiver, a device must be able to handle inbound TLPs with payloads as large as the set value. As a transmitter, the device should not create TLPs with data payloads larger than the MPS setting.

A systems MPS setting is determined during the enumeration and configuration process. Every device in the hierarchy advertises its MPS capability in its Device Capability register, which is located in the devices configuration space. Software probes every device to determine its MPS capability, determines the MPS setting, and programs every device by writing the MPS setting to its Device Control register.

The requested MPS value in the device capability register is set during the CORE Generator customization process.

Maximum Read Request Size

During configuration, the software also programs the maximum read request size into each devices control register. This parameter sets the maximum size of a memory read request, which can be set to a maximum of 4096 bytes in 128-byte increments.

The maximum read request size can be larger than the MPS. For example, a 512-byte read request can be issued to a device with a 128-byte MPS. The device returning the data for the read request limits the size of the Completion with Data TLP to 128 bytes or less, which requires multiple completions for one read. The system uses the maximum read request size to balance the allocation of bandwidth throughout the topology. Limiting the maximum amount of data that a device can read in one transfer prevents it from monopolizing system bandwidth. The maximum read request size also affects performance because it determines how many read requests are required to fetch the data, and read requests are 100% overhead because they do not contain any payload. Reading 64 KB of data using a maximum read request size of 128 bytes requires 512 Memory Read TLPs (64 KB / 128 bytes = 512) to request the data from memory. For efficiency when moving large blocks of data, the size of the read request should be as close as possible to the maximum read request size to reduce the number of reads that must be transmitted.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 36596
Date Created 08/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • More
  • Virtex-6 SXT
  • Spartan-6 LXT
  • Less
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )