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AR# 36627

Design Assistant for PCI Express - Why Are Interrupts Not Transmitted


My design does not generate interrupts. What can I check to debug the issue?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.


For legacy interrupts ensure that the Interrupt Disable bit in the PCI Command register located at offset 0x04 of the Configuration space is set to '0'. It is unusual for this bit to used to disable interrupts, but the host does have the prerogative to do so. The contents of the command register are output to the user on cfg_command[15:0]. To use legacy interrupts, the MSI enable bit must not be set in the MSI control register.

For generation of MSI interrupts ensure the MSI Enable bit is set in the MSI control register. The output cfg_interrupt_msienable will be asserted to 1 if the enable bit is set. Also ensure the bus master enable bit is set in the PCI command register located at offset 0x04 of the configuration space. Again the command register is output to the user on cfg_command[15:0]. If this bit is not set, the core will not transmit the memory write MSI TLP.

See (Xilinx Answer 36594) for more information on enabling interrupts.

Tools such as PCITree or lspci can also be to read the contents of the command or MSI control register. For more information about these types of software tools see (Xilinx Answer 34806). The command register is always located at offset 0x04 but the MSI control register may be located at different locations depending on the core you are using. To find the location of the MSI control register, you can either follow the linked capabilities list or look in the User Guide for the core in use. See (Xilinx Answer 35920) to help locate the correct User Guide. This information will be found the "Core Overview" section.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 36627
Date Created 08/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )