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AR# 36642

Virtex-6 System Monitor - Maximum DCLK frequency revised down to 80 MHz


The initial specification for the DCLK was 250 MHz. This has been revised down to 80 MHz.


The maximum conversion rate of the System Monitor is still 200 ksPs because the ADCCLK is still 5.2 MHz.

The ADCCLK = DCLK / DCLK Divisior (the DCLK divisor is set in the Config Reg #2).

The effect of violating the maximum DCLK of 80 MHz is that it can result in a race condition in the System Monitor logic which results in incorrect readings. The problem occurs at temperatures between 55 C and 80 C only.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A
AR# 36642
Date Created 09/07/2010
Last Updated 05/20/2012
Status Active
Type Design Advisory
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT