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AR# 36741 MIG v3.5, Spartan-6 MCB - Traffic Generator Data Pattern cannot be modified

Description

The Spartan-6 FPGA MIG tool includes a Debug Signal for a Memory Controller option which allows debug signals to be monitored using ChipScope tool. This feature is very useful in hardware testing. The debug signals included are a part of the provided MIG Example Design (Traffic Generator).

In MIG 3.5, the debug port removed the ability to change the data pattern through the VIO ChipScope core. This was done to reduce logic and ensure the debug port was sized appropriately for all Spartan-6 devices. With the previous implementation, enabling the debug port with ChipScope cores caused the design to be too large for smaller Spartan-6 devices (specifically the XC6SLX9).

If users wish to change the data pattern, minor rtl changes can be made to the example design. These changes are detailed in this answer record.

Solution

MIG 3.5 modified the assignment of DATA_PATTERN from DGEN_ALL to DGEN_ADDR. This limits the available data pattern to address as data. See UG416 > Traffic Generator Signal Descriptions for full details on the available data patterns. To enable the ability to use all data patterns in the debug port, modify the following:

1. Open the example_top.v module and modify the cx_vio_data_mode_value:
// assign c3_vio_data_mode_value = 3'b010;
assign c3_vio_data_mode_value = c3_vio_out[5:3] ;

This change allows the data mode to be changed using VIO.

2. Open thee memcx_tb_top.v module and modify the assignment of the DATA_PATTERN parameter:
// .DATA_PATTERN ("DGEN_ADDR"),
.DATA_PATTERN ("DGEN_ALL"),

NOTE: These changes are required to run the SP60x reference design demos in hardware.

Actions

AR# 36741
Date Created 07/13/2010
Last Updated 07/13/2010
Status Active
Type
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
IP
  • MIG
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