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AR# 36749 Design Assistant for PCI Express - Simulation Questions Regarding Transaction Layer Traffic

Description

This Answer Record identifies starting points to debug transaction layer related questions in simulation. However, much of this information is also true in hardware, but is more prevalent in simulation sincethecore generates the rootport simulation model for you.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution


For information on why TLPs might not show up on the user application interface, see (Xilinx Answer 36750). This applies to both root port and endpoint applications.
For information on why TLPs might get corrupted at the MIM interface, see (Xilinx Answer 37752). This applies to both root port and endpoint applications.
Revision History
09/01/2010 - Added (Xilinx Answer 37752)
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38548 Design Assistant for PCI Express - Simulation Traffic Questions N/A N/A
37752 Design Assistant for PCI Express - TLPs are corrupted in simulation N/A N/A
36750 Design Assistant for PCI Express - TLPs are not getting passed to the user application N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 36749
Date Created 07/16/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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