This answer record identifies starting points to debug transaction layer related questions in simulation. However, much of this information is also true in hardware but is more prevalent in simulation since the core generates the Root Port model for you.
Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express
(Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.