To work around this problem, perform the following:
- Edit the pcie_top.v file in the generated core's source directory
- At around line 879, find this line:
localparam [6:0] VC0TOTALCREDITSCH = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? (INFINITECOMPLETIONS ? 0 : 8) : (INFINITECOMPLETIONS ? 0 : 8); // gui - Change it to this:
localparam [6:0] VC0TOTALCREDITSCH = 7'h8; - Find this line:
localparam [10:0] VC0TOTALCREDITSCD = (PORTVCCAPABILITYEXTENDEDVCCOUNT == 0) ? (INFINITECOMPLETIONS ? 0 : 11'h080) : (INFINITECOMPLETIONS ? 0 : 11'h080); // gui - Change it to this:
localparam [10:0] VC0TOTALCREDITSCD = 11'h080; - Save the file and synthesize the design.
To verify that it works, you can run netgen on the synthesized netlist or routed NCD file and check the parameters on the block. For example, if your netlist file is called "endpoint_blk_plus.ngc", the following produces a Verilog file called "endpoint_blk_plus.v".
netgen -ofmt verilog|vhdl endpoint_blk_plus.ngc
Inside this file, search for:
.VCOTOTALCREDITSCD (11'h080),
.VCOTOTALCREDITSCH (7'h08),
Revision History 09/22/2010 - Updated netgen command
07/14/2010 - Initial Release