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AR# 36821

LogiCORE IP Peak Cancellation Crest Factor Reduction (PC-CFR) - What does it mean by the number of iterations?

Description

Whatdoes it mean by the number of iterations for the LogiCORE IP PC-CFR?

Solution

On page 12 of the data sheet, there is a section on "The number of iterations". Generally, this is thenumber of cascaded PC_CFR IP cores needed to meet the requirements. The input data goes into the first PC_CFR IP and the output from the first PC_CFR IP goes into second PC_CFR IP, and so on. Below is an example using the generate statement:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

library UNISIM;
use UNISIM.vcomponents.all;

entity pc_cfr_iteration_top is
port (
clk : in std_logic;
rst : in std_logic;
threshold : in std_logic_vector(15 downto 0);
alloc_sp_0 : in std_logic_vector(9 downto 0);
alloc_sp_1 : in std_logic_vector(9 downto 0);
alloc_sp_2 : in std_logic_vector(9 downto 0);
cpram_ntaps : in std_logic_vector(8 downto 0);
cpram_clk : in std_logic;
cpram_we : in std_logic;
cpram_addr : in std_logic_vector(31 downto 0);
cpram_din : in std_logic_vector(31 downto 0);
din_I : in std_logic_vector(15 downto 0);
din_Q : in std_logic_vector(15 downto 0);
dout_I : out std_logic_vector(15 downto 0);
dout_Q : out std_logic_vector(15 downto 0));
end;

architecture mixed of pc_cfr_iteration_top is

-- Following is the PC_CFR IP component declaration:

component pc_cfr_iteration
port (
aclk: IN std_logic;
areset: IN std_logic;
sparam_threshold: IN std_logic_VECTOR(15 downto 0);
sparam_alloc_spacing: IN std_logic_VECTOR(9 downto 0);
sparam_filter_n_taps: IN std_logic_VECTOR(8 downto 0);
sreg_aclk: IN std_logic;
sreg_areset: IN std_logic;
sreg_awvalid: IN std_logic;
sreg_awready: OUT std_logic;
sreg_awaddr: IN std_logic_VECTOR(31 downto 0);
sreg_wvalid: IN std_logic;
sreg_wready: OUT std_logic;
sreg_wdata: IN std_logic_VECTOR(31 downto 0);
sdata_valid: IN std_logic;
sdata_ready: OUT std_logic;
sdata_i: IN std_logic_VECTOR(15 downto 0);
sdata_q: IN std_logic_VECTOR(15 downto 0);
mdata_valid: OUT std_logic;
mdata_ready: IN std_logic;
mdata_i: OUT std_logic_VECTOR(15 downto 0);
mdata_q: OUT std_logic_VECTOR(15 downto 0);
mstat_data: OUT std_logic_VECTOR(31 downto 0));
end component;

signal sdata_ready : std_logic_vector (31 downto 0);
signal sdata_valid : std_logic_vector (31 downto 0);
signal mdata_ready : std_logic_vector (31 downto 0);
signal mdata_valid : std_logic_vector (31 downto 0);
type array_32x16 is array (0 to 31) of std_logic_vector(15 downto 0);
signal sdata_i : array_32x16;
signal sdata_q : array_32x16;
signal mdata_i : array_32x16;
signal mdata_q : array_32x16;
signal alloc_spacing : array_32x16;

begin

dout_I <= sdata_i(3);
dout_Q <= sdata_q(3);


sdata_i(0) <= din_I;
sdata_q(0) <= din_Q;

alloc_spacing(0)(9 downto 0) <= alloc_sp_0;
alloc_spacing(1)(9 downto 0) <= alloc_sp_1;
alloc_spacing(2)(9 downto 0) <= alloc_sp_2;

-- generate statement for 3 iterations


cfr: for i in 0 to 2 generate
sdata_i(i + 1) <= mdata_i(i);
sdata_q(i + 1) <= mdata_q(i);
sdata_valid(i + 1) <= mdata_valid(i);
mdata_ready(i) <= sdata_ready(i + 1);
unit : pc_cfr_iteration
port map (
aclk => clk,
areset => rst,
sparam_threshold => threshold,
sparam_alloc_spacing => alloc_spacing(i)(9 downto 0),
sparam_filter_n_taps => cpram_ntaps(8 downto 0),
sreg_aclk => cpram_clk,
sreg_areset => '0',
sreg_awvalid => cpram_we,
sreg_awready => open,
sreg_awaddr => cpram_addr,
sreg_wvalid => cpram_we,
sreg_wready => open,
sreg_wdata => cpram_din,
sdata_valid => sdata_valid(i),
sdata_ready => sdata_ready(i),
sdata_i => sdata_i(i),
sdata_q => sdata_q(i),
mdata_valid => mdata_valid(i),
mdata_ready => mdata_ready(i),
mdata_i => mdata_i(i),
mdata_q => mdata_q(i),
mstat_data => open);
end generate;

sdata_valid(0) <= '1';
sdata_ready(3) <= '1';

end;

For LogiCORE IP Peak Cancellation Crest Factor Reduction Release Notes and Known issues, see (Xilinx Answer 33760).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33760 LogiCORE IP Peak Cancellation CFR(PC-CFR) - Release Notes and Known Issues N/A N/A
AR# 36821
Date Created 05/05/2011
Last Updated 12/15/2012
Status Active
Type General Article